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1 p/n:pm0484 rev. 1.6, may. 29, 2000 1. features ? a single chip solution integrates 100/10 base-t fast ethernet mac, phy and pmd ? fully comply to ieee 802.3u specification ? operates over 100 meters of stp and category 5 utp cable ? fully comply to pci spec. 2.1 up to 33mhz ? support full and half duplex operations in both 100base-tx and 10 base-t mode ? magic packet tm mode to support remote-wake-up ? 100/10 base-t nway auto negotiation function ? large on-chip fifos for both transmit and receive operations without external local memory ? bus master architecture with linked host buffers deliv- ers the most optoimized performance ? 32-bit bus master dma channel provides ultra low cpu utilization ? proprietary adaptive network throughput control (antc) technology to optimize data integrity and throughput ? support up to 64k bytes boot rom interface ? three levels of loopback diagnositic capability ? support a variety of flexible address filtering modes with 16 cam address and 512 bits hash ? microwire interface to eeprom for customer's ids and configuration data ? single +5v power supply, standard cmos technol- ogy, 128-pin pqfp package ( magic packet technology is a trademark of advanced micro device corp. ) 2. general descriptions the MX98715EC controller is an ieee802.3u compliant single chip 32-bit full duplex, 10/100mbps highly inte- grated fast ethernet combo solution, designed to ad- dress high performance local area networking (lan) system application requirements. MX98715EC's pci bus master architecture delivers the utilimized performance for future high speed and pow- erful processor technologies. in other words, the MX98715EC not only keeps cpu utilization low while maximizing data throughput, but it also optimizes the pci bandwidth providing the highest pci bandwidth utili- zation. to further reduce maintenance costs the MX98715EC uses drivers that are backward compatible with the original mxic mx98713 series controllers. the MX98715EC contains a pci local bus glueless in- terface, a direct memory access (dma) buffer manage- ment unit, an ieee802.3u-compliant media access con- troller (mac), large transmit and receive fifos, and an on-chip 10 base-t and 100 base-tx transceiver sim- plifying system design and improving high speed signal quality. full-duplex operation are supported in both 10 base-t and 100 base-tx modes that increases the controller's operating bandwidth up to 200mbps. equipped with intelligent ieee802.3u-compliant auto-ne- gotiation, the MX98715EC-based adapter allows a single rj-45 connector to link with the other ieee802.3u-com- pliant device without re-configuration. in MX98715EC, an innovative and proprietary design "adaptive network throughput control" (antc) is built- in to configure itself automatically by mxic's driver based on the pci burst throughput of different pcs. with this proprietary design, MX98715EC can always optimize its operating bandwidth, network data integrity and through- put for different pcs. mxic MX98715EC features remote-wake-up capabil- ity that enables a wide range of wake-up capabilities, including the ability to customize the content of speci- fied packet which pc should to respend to, even when it is in a low-power state. pcs and workstations could take advantage of these capabilities of being waked up and serviced simultaneiously over the network by remote server or workstation. it helps organizations reduce their maintenance cost of high-performance business pcs. with its on-chip support for both little and big endian byte alignment, MX98715EC can also address non-pc applications. MX98715EC single chip fast ethernet nic controller preliminary
2 p/n:pm0484 rev. 1.6, may. 29, 2000 MX98715EC 3. pin configurations 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 bpa4 bpa3 bpa2 bpa1(eedi) bpa0(eeck) eecs bpd0(eed0) bpd1 bpd2 bpd3 bpd4 bpd5 bpd6 bpd7 gnd vdd ad0 ad1 gnd ad2 ad3 vdd ad4 ad5 gnd ad6 vdd gnd gnd vdd gnd vcc gnd nc intab rstb pciclk gntb reqb ad31 ad30 gnd ad29 ad28 vdd ad27 gnd ad26 ad25 gnd ad24 cbeb3 idsel gnd ad23 ad22 gnd ad21 ad20 vdd ad19 ad18 gnd ad17 ad16 cbeb2 frameb gnd irdyb trdyb devselsb stopb vdd perrb serrb pa r cbeb1 ad15 gnd ad14 ad13 vdd ad12 ad11 ad10 gnd ad9 ad8 cbeb0 ad7 rtx rtx2eq cpk gnd txop txon vdd gnd gnd vdd rxip rxin vdd gnd vdd gnd gnd ckref vdd rda gnd vdd led1 led0 bpa15 bpa14 bpa13 gnd vdd bpa12 bpa11 bpa10 bpa9 boeb bpa8 bpa7 bpa6 bpa5 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 MX98715EC
3 p/n:pm0484 rev. 1.6, may. 29, 2000 MX98715EC 4. pin description ( 128 pin pqfp ) ( t/s : tri-state, s/t/s : sustended tri-state, i : input, o : output, o/d : open drain ) pin name type pin no 128 pin function and driver ad[31:0] t/s 116, 117 pci address/data bus: shared pci address/data bus lines. little or big endian 119,120, byte ordering are supported. 122,124, 125,127, 3,4,6,7,9, 10,12,13, 26,28,29, 31-33,35, 36,38,39, 41,42,44, 45,47,48 cbe[3:0] t/s 128,14 pci command and byte enable bus: shared pci command byte enable bus, 25,37 during the address phase of the transaction, these four bits provide the bus command. during the data phase, these four bits provide the byte enable. frameb s/t/s 15 pci frameb signal: shared pci cycle start signal, asserted to indicate the beginning of a bus transaction. as long as frameb is asserted, data transfers continue. trdyb s/t/s 18 pci target ready: issued by the target agent, a data phase is completed on the rising edge of pciclk when both irdyb and trdyb are asserted. irdyb s/t/s 17 pci master ready: indicates the bus master's ability to complete the current data phase of the transaction. a data phase is completed on any rising edge of pciclk when both irdyb and trdyb are asserted. devselb s/t/s 19 pci slave device select: asserted by the target of the current bus access. when 98715 is the initiator of current bus access, the target must assert devselb within 5 bus cycles, otherwise cycle is aborted. idsel i 1 pci initialization device select: target specific device select signal for configuration cycles issued by host. pciclk i 113 pci bus clock input: pci bus clock range from 16mhz to 33mhz. rstb i 112 pci bus reset: host system hardware reset. nc 110 not connected pin intab o/d 111 pci bus interrupt request signal: wired to intab line. serrb o/d 23 pci bus system error signal: if an address parity error is detected and cfcs bit 8 is enabled, serrb and cfcs's bit 30 will be asserted. perrb s/t/s 22 pci bus data error signal: as a bus master, when a data parity error is detected and cfcs bit 8 is enabled, cfcs bit 24 and csr5 bit 13 will be asserted. as a bus target, a data parity error will cause perrb to be asserted.
4 p/n:pm0484 rev. 1.6, may. 29, 2000 MX98715EC pin name type pin no 128 pin function and driver par t/s 24 pci bus parity bit: shared pci bus even parity bit for 32 bits ad bus and cbe bus. stopb s/t/s 20 pci target requested transfer stop signal: as bus master, assertion of stopb cause MX98715EC either to retry, disconnect, or abort. reqb t/s 115 pci bus request signal: to initiate a bus master cycle request gntb i 114 pci bus grant acknowledge signal: host asserts to inform MX98715EC that access to the bus is granted bpa1 o 61 boot prom address bit 1(eecs=0): together with bpa[15:0] to (eedi) access external boot prom up to 256kb. eeprom data in(eecs=1): eeprom serial data input pin. bpa0 o 60 boot prom address bit 0(eecs=0): together with bpa[15:0] to (eeck) access external boot prom up to 256kb. eeprom clock(eecs=1): eeprom clock input pin bpa[15:0] o 78-76, boot prom address line. 73-70, 68-60 bpd0 t/s 58 boot prom data line 0(eecs=0): boot prom or flash data line 0. (eedo) eeprom data out(eecs=1): eeprom serial data outpin(during reset initialization). bpd[7:0] t/s 51-58 boot prom data lines: boot prom or flash data lines 7-0. eecs o 59 eeprom chip select pin. boeb o 69 boot prom output enable. rda o 83 connecting an external resistor to ground, resistor value=10k ohms rtx o 102 connecting an external resistor to ground, resistor value=560 ohms rtx2eq o 101 connecting an external resistor to ground, resistor value=1.4k ohms. cpk i 100 connecting an external capacitor. capacitor value=100pf rxip i 92 twisted pair receive differential input: support both 10 base-t and 100 base-tx receive differential input. rxin i 91 twisted pair receive differential input: support both 10 base-t and 100 base-tx receive differential input txop o 98 twisted pair transmit differential output: support both 10 base-t and 100 base-tx transmit differential output txon o 97 twisted pair transmit differential output: support both 10 base-t and 100 base-tx transmit differential output ckref i 85 reference clock: 25mhz oscillator clock input led0 o 79 programmable led pin 0: csr9.28=1 set the led as link speed (10/100) led. csr9.28=0 set the led as activity led. default is activity led after reset.
5 p/n:pm0484 rev. 1.6, may. 29, 2000 MX98715EC pin name type pin no 128 pin function and driver led1 o 80 programmable led pin 1: csr9.29=1 set the led as link/activity led. csr9.29=0 set the led as good link led. default is good link led after reset. vdd i 8,21,30,43, power pins. 49,74,81,84, 88,90,93,96, 103,106,108, 121 gnd i 2,5,11,16,27 ground pins. 34,40,46,50 75,82,86,87 89,94,95,99 104,105,107 109,118,123 126
6 p/n:pm0484 rev. 1.6, may. 29, 2000 MX98715EC 5. programmong interface 5.1 pci configuration registers: 5.1.1 pci id register ( pfid ) ( offset 03h-00h ) this register can be loaded from external serial eeprom or use a mxic preset value of 10d9 and 0531 for vendor id and device id respectively. word location 3eh and 3dh in serial eeprom are used to configure customer's vendor id and device id respectively. if location 3eh contains"ffff" value then mxic'svendor id and device id will be set in this register, otherwise both 3eh and 3dh will be loaded into this register from serial eeprom. 5.1.2 pci revision register ( pfrv ) ( offset 0bh-08h ) bit 3 - 0 : step number, range from 0 to fh. bit 7 - 4 : revision number, fixed to 2h for MX98715EC bit 15 - 8 : not used bit 23 - 16 : subclass, fixed to 0h. bit 31 - 24 : base class, fixed to 02h. 5.1.3 pci latency timer register ( pflt ) (offset 0fh-0ch) bit 0 - bit 7 : system cache line size in units of 32 bit word, device driver should use this value to program csr0<15:14>. bit 8 - bit 15 : configuration latency timer, when MX98715EC assert frame#, it enables its latency timer to count. if MX98715EC deasserts frame# prior to timer expiration, then timer is ignored. otherwise, after timer expires, MX98715EC initiates transactiontermination as soon as its gnt# is deasserted. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 device id (bit 31:16) vendor id (bit 15:0) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 base class step number subclass revision number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 configuration latency timer system cache line size pflt register (0fh-0ch)
7 p/n:pm0484 rev. 1.6, may. 29, 2000 MX98715EC 5.1.4 pci base io address register ( pbio ) ( offset 13h-10h ) bit 0 : io/memory space indicator, fixed to 1 in this field will map into the io space. this is a read only field. bit 7 - 1 : not used, all 0 when read bit 31 - 8 : defines the address assignment mapping of MX98715EC csr registers. 5.1.4 pci base memory address register ( pbma ) ( offset 17h-14h ) bit 0 : memory space indicator, fixed to 0 in this field will map into the memory space. this is a read only field. bit 6 - 1 : not used, all 0 when read bit 31 - 7 : defines the address assignment mapping of MX98715EC csr registers. 5.1.5 pci subsystem id register ( psid ) ( offset 2ch-2fh ) this register is used to uniquely identify the add-on board or subsystem where the nic controller resides. values in this register are loaded directly from external serial eeprom after system reset automatically. word location 36h of eeprom is subsystem vendor id and location 35h is sub-system id. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 configuration base memory address memory spec indicator 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 subsystem id (31:16) subsystem vendor id (bit 15:0) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 configuration base io address io/memory spec indicator
8 p/n:pm0484 rev. 1.6, may. 29, 2000 MX98715EC 5.1.6 pci base expansion rom address register ( pber ) ( offset 33h-30h ) bit 0 : address decode enable, decoding will be enabled if only both enable bit in pfcs<1> and this expansion rom register are 1. bit 10 - 1 : not use bit 31 - 11 : defines the upper 21 bits of expansion rom base address. 5.1.7 interrupt register ( pfit ) ( offset 3fh-3ch ) bit 7 - 0 : interrupt line, system bios will writes the routing information into this field, driver can use this information to determine priority and interrupt vector. bit 15 - 8 : interrupt pin, fixed to 01h which use inta#. bit 31 - 24 : max_lat which is a maximum period for a access to pci bus. bit 23 - 16 : min_gnt which is the maximum period that MX98715EC needs to finish a brust pci cycle. 5.1.8 pci driver area register ( pfda ) ( 43h-40h ) bit 31 : sleep mode, set to sleep mode which allows access to pci configuration space, a hardware reset or reset to this bit can exit from sleep mode. magic packet can be received under sleep mode if csr16<21> ( magic packet enable ) is set. bit 30 : not used bit 29 : board type bit 15 - 8 : driver is free to read and write this field for any purpose. bit 7 - 0 : not used. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 min-gnt interrupt pin max_lat 0 0 1 1 1 0 0 0 0 0 0 0 1 0 0 0 interrupt line 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 expansion rom base address (upper 21 bit) address decode enable 0 0 0 0 0 0 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 sleep mode board type driver special use
9 p/n:pm0484 rev. 1.6, may. 29, 2000 MX98715EC 5.2 host interface registers MX98715EC csrs are located in the host i/o or memory address space. the csrs are double word aligned and 32 bits long. definitions and address for all csrs are as follows : csr mapping register meaning offset from csr base address ( pbio and pbma ) csr0 bus mode 00 csr1 transmit poll demand 08h csr2 receive poll demand 10h csr3 receive list demand 18h csr4 transmit list base address 20h csr5 interrupt status 28h csr6 operation mode 30h csr7 interrupt enable 38h csr8 missed frame counter 40h csr9 serial rom and mii management 48h csr10 reserved 50h csr11 general purpose timer 58h csr12 10 base-t status port 60h csr13 sia reset register 68h csr14 10 base-t control port 70h csr15 watchdog timer 78h csr16 magic packet register 80h csr20 nway status register a0h
10 p/n:pm0484 rev. 1.6, may. 29, 2000 MX98715EC 5. 2.1 bus mode register ( csr0 ) field name description 0 swr software reset, when set, MX98715EC resets all internal hardware with the exception of the configuration area and port selection. 1 bar internal bus arbitration scheme between receive and transmit processes. the receive channel usually has higher priority over transmit channel when receive fifo is partially full to a threshold. this threshold can be selected by programming this bit. set for lower threshold, reset for normal threshold. 6:2 dsl descriptor skip length, specifies the number of longwords to skip between two descrip- tors. 7 ble big/little endian, set for big endian byte ordering mode, reset for little endian byte order- ing mode, this option only applies to data buffers 13:8 pbl programmable burst length, specifies the maximum number of longwords to be t r ans- ferred in one dma transaction. default is 0 which means unlimited burst length, possible values can be 1,2,4,8,16,32 and unlimited . 15:14 cal cache alignment, programmable address boundaries of data burst stop, MX98715EC can handle non-cache- aligned fragement as well as cache-aligned fragment efficiently. 18:17 tap tr ansmit auto-polling time interval, defines the time interval for MX98715EC to performs transmit poll command automatically at transmit suspended state. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 tap-transmit automatic polling zero-must be zero dsl-descriptor skip length swr-software reset cal-cache alignment pbl-programmable burst length ble-big/little endian bar-bus arbitration 0 table 5.2.0 transmit auto polling bits csr<18:17> time interval 00 no transmit auto-polling, a write to csr1 is required to poll 01 auto-poll every 200 us 10 auto-poll every 800 us 11 auto-poll every 1.6 ms
11 p/n:pm0484 rev. 1.6, may. 29, 2000 MX98715EC 5.2.2 transmit poll command ( csr1 ) field name description 31:0 tpc w rite only, when written with any value, MX98715EC read transmit descriptor list in host memory pointed by csr4 and processes the list. 5.2.3 receive poll command ( csr2 ) field name description 31:0 rpc w rite only, when written with any value, MX98715EC read receive descriptor list in host memory pointed by csr4 and processes the list. 5.2.4 descriptor list address ( csr3, csr4 ) csr3 receive list base address csr4 traansmit list base address 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 transmit poll command 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 receive poll command 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 start of receive list address 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 start of transmit list address
12 p/n:pm0484 rev. 1.6, may. 29, 2000 MX98715EC 5.2.5 status register ( csr5 ) field name description 28 mpi magic packet received interrupt. valid only if csr16<22> bit is set. 27 lc 100 base-tx link status has changed either from pass to fail or fail to pass. read csr12<1> for 100 base-tx link status. 25:23 eb error bits, read only, indicating the type of error that casued fatal bus error. 22:20 ts transmit process state, read only bits indicating the state of transmit process. 19:17 rs receive process state, read only bits indicating the state of receive process. 16 nis normal interrupt summary, is the logical or of csr5<0>, csr5<2> and csr5<6> and csr5<28>. 15 ais abnormal interrupt summary, is the logical or of csr5<1>, csr5<3>, csr5<5>, csr5<7>, csr5<8>, csr5<9>, car5<10>, csr5<11> and csr5<13>, csr5<27>. 14 eri early receive interrupt, indicating the first buffer has been filled in ring mode, or 64 bytes has been received in chain mode. 13 fbe fatal bus error, indicating a system error occured, MX98715EC will disable all bus ac- cess. 12 lf link fail, indicates a link fail state in 10 base-t port. this bit is valid only when csr6<18>=0, csr14<8>=1, and csr13<3>=0. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rs-receive process state nis-normal interrupt summary lf-link fail eti-early transmit interrupt ais-abnormal interrupt summary eri-early receive interrupt fbe-fatal bus error gte-general purpose timer expired mpi-magic packet interrupt lc-link change rps-receive process stopped ri-receive interrupt eb-error bits ts-transmit process state rwt-receive watchdog timeout ru-receive buffer unavailable lpaci-link pass/autonegotiation completed interrupt unf-transmit underflow tjt-transmit jabber timeout tu-transmit buffer unavailable tps-transmit process stopped ti-transmit interrupt
13 p/n:pm0484 rev. 1.6, may. 29, 2000 MX98715EC 11 gte general purpose timer expired, indicating csr11 counter has expired. field name description 10 eti early transmit interrupt, indicating the packet to be transmitted was fully transferred to internal tx fifo. csr5<0> will automatically clears this bit. 9 rwt receive watchdog timeout, reflects the network line status where receive watchdog timer has expired while the other node is still active on the network. 8 rps write only, when written with any value, MX98715EC reads receive descriptor list in host memory pointed by csr4 and processes the list. 7 ru receive buffer unavailable, the receive process is suspended due to the next descriptor in the receive list is owned by host. if no receive poll command is issued, the reception process resumes when the next recognized incoming frame is received. 6 ri receive interrupt, indicating the completion of a frame reception. 5 unf transmit underflow, indicating transmit fifo has run empty before the completion of a packet transmission. 4 lpanci when autonegotiation is not enabled ( csr14<7>=0 ), this bit indicates that the 10 base- t link integrity test has completed successfully, after the link was down. this bit is also set as as a result of writing 0 to csr14<12> ( link test enable ). when autonegotiation is enabled ( csr14<7> =1 ) , this bit indicates that the autonegotiation has completed ( csr12<14:12>=5 ). csr12 should then be read for a link status report. this bit is only valid when csr6<18>=0, i.e. 10 base-t port is selected link fail interrupt ( csr5<12> ) will automatically clears this bit. 3 tjt transmit jabber timeout, indicating the MX98715EC has been excessively active. the transmit process is aborted and placed in the stopped state. tdes0<1> is also set. 2 tu transmit buffer unavailable, transmit process is suspended due to the next descriptor in the transmit list is owned by host. 1 tps transmit process stopped. 0 ti transmit interrupt. indicating a frame transmission was completed.
14 p/n:pm0484 rev. 1.6, may. 29, 2000 MX98715EC table 5.2.1 fatal bus error bits csr5<25:23> process state 000 parity error for either serr# or perr#, cleared by software reset. 001 master abort 010 target abort 011 reserved 1xx reserved table 5.2.2 transmit process state csr5<22:20> process state 000 stopped- reset or transmit jabber expired. 001 fetching transmit descriptor 010 waiting for end of transmission 011 filling transmit fifo 100 reserved 101 setup packet 110 suspended, either fifo underflow or unavailable transmit descriptor 111 closing transmit descriptor table 5.2.3 receive process state csr5<19:17> process state 000 stopped- reset or stop receive command fetching receive descriptor 010 checking for end of receive packet 011 waiting for receive packet 100 suspended, receive buffer unavailable 101 closing receive descriptor 110 purging the current frame from the receive fifo due to unavailable receive buffer 111 queuing the receive frame from the receive fifo into host receive buffer
15 p/n:pm0484 rev. 1.6, may. 29, 2000 MX98715EC 5.2.6 operation mode register ( csr6 ) field name description 24 scr scrambler mode, default is set to enable scrambler function. not affected by software reset. 23 pcs default is set to enable pcs functions. csr6<18> must be set in order to operate in symbol mode. 22 ttm transmit threshold mode, set for 10 base-t and reset for 100 base-tx. 21 sf store and forward, when set, transmission starts only if a full packet is in transmit fifo. the threshold values defined in csr6<15:14> are ignored 19 hbd heartbeat disable, set to disable sqe function in 10 base-t mode. 18 ps port select, deafult is 0 which is 10 base-t mode, set for 100 base-tx mode. a software reset does not affect this bit. 17 coe collision offset enable, set to enable a modified backoff algorithm during low collision situation, reset for normal backoff algorithm. 15:14 tr threshold control bits, these bits controls the selected threshold level for MX98715EC stransmit fifo, transmission starts when frame size within the transmit fifo is larger than the selected threshold. full frames with a length less than the threshold are also transmitted. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 coe-collision offset enable fc-force collision mode lom-loopback operation mode tr-threshold control bits st-start/stop transmission command ttm-transmit threshold mode sf-store and forward pr-promiscuous mode hbd-hearbeat disable ps-port select fd-full duplex mode pm-pass all multicast sb-start/stop backoff counter if-inverse filtering pb-pass bad frame ho-hash-only filtering mode sr-start/stop receive hp-hash/perfect receive filtering mode pcs-pcs function scr-scrambler mode
16 p/n:pm0484 rev. 1.6, may. 29, 2000 MX98715EC field name description 13 st start/stop transmission command, set to place transmission process in running state and will try to transmit current descriptor in transmit list. when reset, transmit process is placed in stop state. 12 fc force collision mode, used in collision logic test in internal loopback mode, set to force collision during next transmission attempt. this can result in excessive collision reported in tdes0<8> if 16 or more collision. 11:10 lom loopback operation mode, see table. 9 fd full-duplex mode, set for simultaneous transmit and receive operation, heart beat check is disabled, tdes0<7> should be ignored, and internal loopback is not allowed. this bit controls the value of bit 6 of link code word . 7 pm pass all multicast, set to accept all incoming frames with a multicast destination address are received. incoming frames with physical address are filtered according to the csr6<0> bit. 6 pr promiscuous mode, any incoming valid frames are accepted, default is reset and not affected by software reset. 5 sb start/stop backoff counter, when reset, the backoff timer is not affected by the network carrier activity. otherwise, timer will start counting when carrier drops. 4 if inverse filtering, read only bit, set to operate in inverse filtering mode, only valid during perfect filtering mode. 3 pb pass bad frames, set to pass bad frame mode, all incoming frames passed the address filtering are accepted including runt frames, collided fragments, truncated frames caused by fifo overflow. 2 ho hash-only filtering mode , read only bit, set to operate in imperfect filtering mode for both physical and multicast addresses. 1 sr start/stop receive, set to place receive process in running state where descriptor acqui- sition is attempted from current position in the receive list. reset to place the receive process in stop state. 0 hp hash/perfect receive filtering mode, read only bit, set to use hash table to filter multicast incoming frames. if csr6<2> is also set, then the physical addresses are imperfect ad- dress filtered too. if csr6<2> is reset, then physical addresses are perfect address fil- tered, according to a single physical address as specified in setup frame.
17 p/n:pm0484 rev. 1.6, may. 29, 2000 MX98715EC table 5.2.4 transmit threshold csr6<21> csr6<15:14> csr6<22>=0 csr6<22>=1 (threshold bytes) (for 100 base-tx) (for 10 base-t) 0 00 128 72 0 01 256 96 0 10 512 128 0 11 1024 160 1 xx ( store and forward ) table 5.2.5 data port selection csr14<7> csr6<18> csr6<22> csr6<23> csr6<24> port 1 0 x x x nway auto-negotiation 0 0 10 base-t 0 1 0 1 1 100 base-tx table 5.2.6 loopback operation mode csr6<11:10> operation mode 00 normal 01 internal loopback at fifo port 11 internal loopback at the phy level 10 external loopback at the pmd level table 5.2.7 filtering mode csr6<7> csr6<6> csr6<4> csr6<2> csr6<0> filtering mode 0 0 0 0 0 16 perfect filtering 0 0 0 0 1 512-bit hash + 1 perfect filtering 0 0 0 1 1 512-bit hash for multicast and physical addresses 0 0 1 0 0 inverse filtering x 1 0 0 x promiscuous 0 1 0 1 1 promiscuous 1 0 0 0 x pass all multicast 1 0 0 1 1 pass all multicast
18 p/n:pm0484 rev. 1.6, may. 29, 2000 MX98715EC 5.2.7 interrupt mask register ( csr7 ) field name description 28 mpie magic packet interrupt enable, enables csr5<28>. 27 lce link changed enable, enables csr5<27>. 16 nie normal interrupt summary enable, set to enable csr5<0>, csr5<2>, csr5<6>. 15 aie abnormal interrupt summary enable, set to enbale csr5<1>, csr5<3>, csr5<5>, csr5<7>, csr5<8>, csr5<9>, csr5<11> and csr5<13>. 14 erie early receive interrupt enable 13 fbe fatal bus error enable, set together with with csr7<15> enables csr5<13>. 12 lfe link fail interrupt enable, enables csr5<12> 11 gpte general purpose timer enable, set together with csr7<15> enables csr5<11>. 10 etie early transmit interrupt enable, enables csr5<10> 9 rwe receive watchdog timeout enable, set together with csr7<15> enables csr5<9>. 8 rse receive stopped enable, set together with csr7<15> enables csr5<8>. 7 rue receive buffer unavailable enable, set together with csr7<15> enables csr5<7>. 6 rie receive interrupt enable, set together with csr7<16> enables csr5<6>. 5 une underflow interrupt enable, set together with csr7<15> enables csr5<5>. 4 lpancie link pass/autonegotiation completed interrupt enable 3 tje transmit jabber timeout enable, set together with csr7<15> enables csr5<3>. 2 tue transmit buffer unavailable enable, set together with csr7<16> enables csr5<2>. 1 tse transmit stop enable, set together with csr7<15> enables csr5<1>. 0 tie transmit interrupt enable, set together with csr7<16> enables csr5<0>. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 nie-normal interrupt summary enable fbe-fatal bus error enable lfe-link fail enable aie-abnormal interrupt summary enable erie-early receive interrupt enable etie-early transmit interrupt enable rie-receive interrupt enable rwe-receive watchdog enable rse-receive stopped enable gpte-general-purpose timer enable rue-receive buffer unavailable enable une-underflow interrupt enable lpancie-link pass /nway complete interrupt enable tje-transmit jabber timeout enable tue-transmit buffer unavailable enable tse-transmit stopped enable tie-transmit interrupt enable lce-link changed enable mpie-magic packet interrupt enable
19 p/n:pm0484 rev. 1.6, may. 29, 2000 MX98715EC 5.2.8 missed frame counter ( csr8 ) field name description 16 mfo missed frame overflow, set when missed frame counter overflows, reset when csr8 is read. 15:0 mfc missed frame counter, indicates the number of frames discarded because no host receive descriptors were available. 5.2.9 non-volatile memory control register ( csr9 ) field name description 29 led1sel 0:default value. set led1 as good link led 1: set led1 as link/activity led. 28 led0sel 0:default value. set led0 as activity led. 1: set led0 as link speed (10/100) led. 14 rd boot rom read operation when boot rom is selected. 12 br boot rom select, set to select boot rom only if csr9<11>=0. 11 sr serial rom select, set to select serial rom for either read or write operation. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 missed frame overflow missed frame counter 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 br-boot rom select data-boot rom data or serial rom control led1sel led0sel rd-read operation sr-serial rom select
20 p/n:pm0484 rev. 1.6, may. 29, 2000 MX98715EC field name description 7:0 data if boot rom is selected ( csr9<12> is set ), this field contains the data to be read from and written to the boot rom. if serial rom is selected , csr9<3:0> are defined as fol- lows: 3 sdo serial rom data out from serial rom into MX98715EC. 2 sdi serial rom data input to serial rom from MX98715EC. 1 sclk serial clock output to serial rom. 0 scs chip select output to serial rom. warning : csr9<11> and csr9<12> should be mutually exclusive for correct operations. 5.2.10 general purpose timer ( csr11 ) field name description 16 con when set,the general purpose timer is in continuous operating mode. when reset, the timer is in one-shot mode. 15:0 timer value contains the timer value in a cycle time of 204.8us. 5.2.11 10 base-t status port ( csr12 ) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 con-continuous mode timer value 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 lpc-link partner's link code word lpn-link partner negotiable ans-autonegotiation arbitration state trf-transmit remote fault aps-autopolarity state ls10-link status of 10 base-t ls100-link status of 100 base-tx *software reset has no effect on this register
21 p/n:pm0484 rev. 1.6, may. 29, 2000 MX98715EC field name decription 31:16 lpc link partner's link code word, where bit 16 is s0 ( selector field bit 0 ) and bit31 is np ( next page ). effective only when csr12<15> is read as a logical 1. 15 lpn link partner negotiable, set when link partner support nway algorithm and csr14<7> is set. 14:12 ans autonegotiation arbitration state, arbitration states are defined 000 = autonegotiation disable 001 = transmit disable 010 = ability detect 011 = acknowledge detect 100 = complete acknowledge detect 101 = flp link good; autonegotiation complete 110 = link check when autonegotiation is completed, an anc interrupt ( csr5<4>) is generated, write 001 into this field can restart the autonegotiation sequence if csr14<7> is set. other- wise, these bits should be 0. 11 trf transmit remote fault 3 aps autopolarity state, set when polarity is positive. when reset, the 10base-t polarity is negative. the received bit stream is inverted by the receiver. 2 ls10 set when link status of 10 base-t port link test fail. reset when 10 base-t link test is in pass state. 1 ls100 link state of 100 base-tx, this bit reflects the state of sd pin, effective only when csr6<23>= 1 ( pcs is set ). set to indicate a fail condition .i.e. sd=0. 5.2.12 sia reset register (csr13) field name decription 0 nway reset while writing 0 to this bit, resets the csr12 & csr14. 1 100base-tx reset write a 1 will reset the internal 100 base-tx phy module 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 100 tx reset- 100 base-tx phy level reset nway reset- nway and 10 base-t phy level reset
22 p/n:pm0484 rev. 1.6, may. 29, 2000 MX98715EC 5.2.13 10 base-t control port (csr14) field name decription 18 t4 bit 9 of link code word for t4 mode. 17 txf bit 8 of link code word for 100 base-tx full duplex mode. 16 txh bit 7 of link code word for 100 base-tx half duplex mode. meaningful only when csr14<7> ( ane ) is set. 12 lte link test enable, when set the 10 base-t port link test function is enabled. 8 rsq receive squelch enable for 10 base-t port. set to enable. 7 ane autonegotiation enable, . 6 hde half-duplex enable, this is the bit 5 of link code word, only meaningful when csr14<7> is set. 2 pwd10 set to power down 10 base-t module, this will force both tx and rx port into tri-state and prevent ac current path. reset for normal 10 base t operation. 1 lbk loop back enable for 10 base-t mcc. 5.2.14 watchdog timer ( csr15) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 t4-100 base-t4 (link code word) txf-100 base-tx full duplex (link code word) txh-100 base-tx half duplex (link code word) lte-link test enable rso-receive squelch enable ane-autonegotiation enable hde-half duplex enable) pwd10-power down 10 base-t lbk-loopback (mcc) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 mbz-must be zero rwr-receive watchdog release pwd-receive watchdog disable jck-jabber clock huj-host unjabber jab-jabber disable
23 p/n:pm0484 rev. 1.6, may. 29, 2000 MX98715EC field name description 5 rwr defines the time interval no carrier from receive watchdog expiration until reenabling the receive channel. when set, the receive watchdog is release 40-48 bit times from the last carrier deassertion. when reset, the receive watchdog is released 16 to 24 bit times from the last carrier deassertion. 4 rwd when set, the receive watchdog counter is disable. when reset, receive carriers longer than 2560 bytes are guaranted to cause the watchdog counter to time out. packets shorter than 2048 bytes are guaranted to pass. 2 jck when set, transmission is cut off after a range of 2048 bytes to 2560 bytes is transmitted, when reset, transmission for the 10 base-t port is cut off after a range of 26 ms to 33ms. when reset, transmission for the 100 base-tx port is cut off after a range of 2.6ms to 3.3ms. 1 huj defines the time interval between transmit jabber expiration until reenabling of the trans- mit channel. when set, the transmit channel is released immediately after the jabber expiration. when reset, the jabber is released 365ms to 420 ms after jabber expiration for 10 base-t port. when reset, the jabber is released 36.5ms to 42ms after the jabber exporation for 100 base-tx port. 0 jbd jabber disable, set to disable transmit jabber function. 5 . 2.15 magic packet register ( csr16 ) field name description bit 31:23 reserved bit 15:0 reserved bit 22 mpe magic packet enable, set to enable magic packet mode sleep mode and mpe mode can be used seperately. when sleep and mpe are both set, the sleep mode dominate mpe, i.e., no magic packet can be detected since both tx and rx channel are shut off in sleep mode. on the detection of magic packet, the mpi interrupt bit at csr5<28> can be set to generate a pci interrupt if csr7<28> mpie is set. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 mpe (magic packet enable)
24 p/n:pm0484 rev. 1.6, may. 29, 2000 MX98715EC 6. ac/dc characteristics 6.1 boot rom read timing trc bpa 15-0 toes tce bceb boeb (ce&oe is typical shorted) toh bpd 7:0 tac c toolz tcolz toh 5.2.16 nway status register ( csr20 ) field name description 31 t4 t4 mode is accepted, read only 30 100txf 100base-tx full duplex is accepted, read only 29 100txh 100base-tx half duplex is accepted, read only 28 10txf 10base-t duplex is accepted, read only 27 10txh 10base-t half duplex is accepted, read only 16 reserved reserved for test purpose, must be set 1 for normal operation. 12 reserved reserved for test purpose, must be set 1 for normal operation. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 100t4 100txf 100txh 10txf 10txh reserved reserved
25 p/n:pm0484 rev. 1.6, may. 29, 2000 MX98715EC 6.2 ac characteristics symbol description minimum typical maximum units trc read cycle 8 - - pci cycle tce chip enable access time - - 7 pci cycle tacc address access time - - 7 pci cycle toes output enable access time - - 7 pci cycl toh output hold from address, ceb, or oeb 0 - - ns pci cycle range:66ns (16mhz)~25ns (40mhz) 6.3 absolute operation condition supply voltage (vcc) -0.5v to +7.0v dc input voltage (vin) 4.75v to 5.25v dc output voltage (vout) -0.5v to vcc + 0.5v storage temperature range (tstg) -55oc to +150oc operating temperature range 0oc to 70oc power dissipation (pd) 750mw (typ) lead temp. (tl) (soldering, 10 sec) 260oc esd rating (rzap = 1.5k, czap = 100pf) 1.0kv clamp diode current 20ma 6.4 dc characteristics symbol parameter conditions min max units ttl/pci input/output voh minimum high level output voltage ioh = -3ma 2.4 v vol maximum low level output voltage iol = +6ma 0.4 v vih minimum high level input voltage 2.0 v vil maximum low level input voltage 0.8 v iin input current vi = vcc or gnd - 1.0 + 1.0 ua ioz minimum tri-state output leakage current vout = vcc or gnd -10 +10 ua led output driver vlol led turn on output voltage iol = 16ma 0.4 v supply idd average supply current ckref =25mhz 130 170 ma pciclk = 33mhz vdd average supply voltage 4.75v 5.25v v
26 p/n:pm0484 rev. 1.6, may. 29, 2000 MX98715EC 7.0 package information 128-pin plastic quad flat pack a e l a1 l1 e3 a e 38 1 64 65 102 103 128 39 i h d3 d zd b c d ze item millimeters inches a 14.00 .05 5.512 .002 b .20 [typ.] .08 [typ.] c 20.00 .05 7.87 .002 d 1.346 .530 e .50 [typ.] .20 [typ.] l1 1.60 .1 .63 .04 l .80 .1 .31 .04 ze .75 [typ.] .30 [typ.] e3 12.50 [typ.] 4.92 [typ.] e 17.20 .2 6.77 .08 zd .75 [typ.] .30 [typ.] d3 18.50 [typ.] 7.28 [typ.] d 23.20 .2 9.13 .08 a1 .25 .1 min. .01 .04 min. a 3.40 .1 max. 1.34 .04 max. note short lead short lead note: each lead centerline is located within .25 mm[.01 inch] of its true position [tp] at maximum material condi- tion.
27 p/n:pm0484 rev. 1.6, may. 29, 2000 MX98715EC revision history revision destription page date 1.5 (1) revise pfrv register bit 31-24 to be 2h 6 sep/15/1998 (2) exchange description for pfit register bit 7-0 and bit 15-8 8 (3) revise esd rating in section 6.3 from 1.5kv to 1.0kv 25 (4) add power dissipation in section 6.3 to be 750mw (typ) 25 (5) add idd value in section 6.4 to be 130 ma to 170ma 25 1.6 modify mx98715 --> MX98715EC may/29/2000
m acronix i nternational c o., l td. headquarters: tel:+886-3-578-6688 fax:+886-3-563-2888 europe office: tel:+32-2-456-8020 fax:+32-2-456-8021 japan office: tel:+81-44-246-9100 fax:+81-44-246-9105 singapore office: tel:+65-348-8385 fax:+65-348-8096 taipei office: tel:+886-2-2509-3300 fax:+886-2-2509-2200 m acronix a merica, i nc. tel:+1-408-453-8088 fax:+1-408-453-8488 chicago office: tel:+1-847-963-1900 fax:+1-847-963-1909 http : //www.macronix.com macronix international co., ltd. reserves the right to change product and specifications without notice. 28 MX98715EC MX98715EC c9930 tdta777001 taiwan line 1 : mx98715 is mxic parts no. "e" :pqfp "c" : commercial grade line 2 : assembly date code. line 3 : wafer lot no. line 4 : state top side marking

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